- Boston, Massachusetts, United States
- Hybrid
- Full-time · Senior
- $154K–$218K per year
- 5+ years
Develop RTL (SystemVerilog) modules for ASIC design, debug complex logic and mixed-signal simulations, integrate silicon photonic communication into digital accelerator design, and collaborate across architecture, verification, physical design, photonic, analog, and software teams.
Compensation
$154,000—$218,000 USD
Responsibilities
- Develop RTL modules with DFT considerations for IC development
- Debug complex logic and mixed signal simulations
- Integrate silicon photonic communication and compute technology into digital accelerator design
- Collaborate with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams
- Create design specifications and documentation
Requirements
- Bachelor’s degree in Electrical or Computer Engineering (or related fields)
- Nice to have: Master's degree in Electrical or Computer Engineering
- Nice to have: PCIe
- Nice to have: processor design
- Nice to have: accelerators