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1–2 jobs· newest first

ASIC Design Engineer, GPU Core Pipeline IPNew
NVIDIA · Bengaluru, India
Hybrid
ASIC Design Engineer, GPU Core Pipeline IPNew
NVIDIA · Bengaluru, India
Hybrid

+10K new in the last hour

ASIC Design Engineer, GPU Core Pipeline IP

NVIDIA · Posted Nov 11, 2026

Bengaluru, Karnataka, India
Hybrid
3+ years

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Design and implement the next generation of control subsystems for NVIDIA GPUs, focusing on micro‑architecture and RTL design of ASICs.

Responsibilities

Design and implement graphics and compute features within an IP
Develop RTL using Verilog/SystemVerilog
Collaborate with architecture, verification and physical design teams
Ensure designs meet performance, power, area, and timing goals
Participate in silicon bring‑up, post‑silicon debug, and performance analysis

Requirements

Bachelor's in Engineering
Master's in Engineering
Nice to have: 3D graphics processing
Nice to have: processor design
Nice to have: C/C++ programming

Skills

Verilog SystemVerilog C++OOP RTL design micro‑architecture development digital design fundamentals synchronous design timing closure clock/reset methodologies computer architecture concepts ASIC design methodologies simulation tools debug tools Perl Python

Benefits

competitive salaries
generous benefits package

See full job description

ASIC Design Engineer, GPU Core Pipeline IP

NVIDIA · Posted Nov 11, 2026

Bengaluru, Karnataka, India
Hybrid
3+ years

Apply with RefersoAI Apply on careers page

Design and implement GPU ASIC control subsystems, RTL design, micro-architecture, and participate in silicon bring-up and performance analysis.

Responsibilities

Design and implement graphics and compute features within an IP
Develop RTL using Verilog/SystemVerilog
Collaborate with architecture, verification, and physical design teams
Ensure designs meet performance, power, area, and timing goals
Participate in silicon bring-up, post-silicon debug, and performance analysis

Requirements

B.Tech.
M.Tech.
Nice to have: 3D graphics processing
Nice to have: processor design
Nice to have: Perl

Skills

Verilog SystemVerilog C++RTL design micro-architecture development digital design fundamentals synchronous design

clock/reset methodologies

computer architecture concepts

ASIC design methodologies

See full job description