- Haifa, Haifa District, Israel +1 more
- On-site
- 2+ years
ASIC STA Engineer responsible for timing sign-off, flow development, and constraint ownership across SoC design.
Locations (2)
- Haifa, Haifa District, Israel
- Herzliya, Tel Aviv, Israel
Responsibilities
- Develop timing sign-off and STA flow
- Own full chip, IP, and block level timing constraints
- Collaborate with RTL, CAD, and Physical design teams
- Generate and manage SDC constraints
- Script in Tcl and Perl
Requirements
- B.Sc / M.Sc in Electrical or Computer Engineering