Technical leadership for ASIC development focusing on fullchip floorplan, RTL-to-GDSII implementation, and physical design.
Compensation
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
Handson experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks
A Design/SDC Engineer focused on timing constraints, SDC/STA tools, and seamless physical design closure for next-generation networking chips.
Responsibilities
Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Requirements
Bachelor’s Degree in Electrical or Computer Engineering
Master’s Degree in Electrical or Computer Engineering
The base salary range is $140,000 - $156,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.
Responsibilities
Responsible for floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level.
Deliver tape-out quality GDSII with silicon success in sub 10 nm.
Requirements
BS/MS in EE/computer science or equivalent experience
Nice to have: experience with Cadence Innovus/Genus/Conformal
Nice to have: experience with Synopsys Primetime/StarRC
An ASIC Design for Test Engineer role focused on Design-for-Test (DFT) within the Silicon One team creating hardware platforms.
Compensation
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, and/or training.
Responsibilities
Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
Create and enhance automation scripts to improve implementation robustness and efficiency.
Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog.
Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.
Requirements
Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months)
A successful candidate will join a team designing and developing Lattice FPGA software tools at Penang. The candidate will contribute to research, design and development of FPGA Foundation IP and IP Catalog tooling.
Responsibilities
Design and implement Digital Signal Processor (DSP) DSP-centric foundation IP blocks, including multipliers, accumulators, FIR/IIR filter primitives, and arithmetic units targeted for integration into FPGA fabric
Develop RTL (VHDL/Verilog/SystemVerilog) for DSP hard macros and programmable DSP slices
Perform functional simulation and timing analysis to ensure correctness and performance targets are met
Engage with software and tools teams to ensure DSP IP is correctly modeled in simulation libraries and synthesis flows
Maintain existing software product tools and develop improvement plan to increase the test coverage to achieve high product quality
Requirements
Bachelor's or Master's degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline
Nice to have: functional verification methodologies
Nice to have: SystemVerilog Assertions
Nice to have: formal verification
Nice to have: synthesis and static timing analysis tools
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