Referso Jobs

FW Design Eng 2

Lattice Semiconductor · Posted Aug 31, 2026

Open

Pune, Maharashtra, India
3+ years

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FW Design Eng 2

Lattice Semiconductor · Posted Aug 31, 2026

Open

Pune, Maharashtra, India
3+ years

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FY27 Intern - PMU Internship - 6 months, Cambridge

Qualcomm · Posted Nov 6, 2026

Open

Cambridge, Cambridgeshire, United Kingdom
On-site
Internship · Intern

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Summer placement aimed at looking at the possible solution to reduce the deep sleep current and/or reduce the external component count in our future products. The project involves understanding the needs of reducing the deep sleep current and/or reducing the external component count in the analog blocks, coming up with the idea for the system level solution and coming up with the architecture for the blocks.

Responsibilities

work under the direction of a senior member of staff
complete and document the tasks so that the designs can be reused in future products
design blocks and prove them in a test-chip in a deep sub-micron process

Requirements

Post-graduate

Skills

Device physics CMOS technology CMOS process design skills

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Senior Engineer, HIG-HBM Product Engineering (Media Health Reliability)

Micron Technology · Posted Nov 6, 2026

Open

Singapore, Singapore, Singapore
Full-time · Senior
5+ years

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Senior Engineer role focused on reliability test flow development, DPM reduction, and root cause analysis for HBM products, utilizing AI and machine learning to enhance product qualification workflows.

Responsibilities

Define and develop reliability stress, test flows and test plans to cover all Product Reliability aspects.
Work closely with Global Quality team to define qualification plan, review and manage the qualification execution progress, and drive for qualification gating issue resolution.
Drive down and achieving Extrinsic Reliability and Intrinsic Reliability through Optimized Manufacturing Test Flows and Test Strategy.
Debug and identify root cause and failures in reliability tests by electric failure analysis(EFA) and Physical Failure Analysis (PFA).
Provide recommendation to fab teams for new process conversions to reduce cost and increase yields.

Requirements

Bachelor’s or Master’s degree in Electrical and Electronics Engineering or a related field
Nice to have: Semiconductor devices
Nice to have: Circuit design
Nice to have: Product validation

Skills

Semiconductor industry Product testing Reliability experience

Senior Engineer, HIG-HBM Product Engineering (Media Health Reliability)

Micron Technology · Posted Nov 6, 2026

Open

Singapore, Singapore
Senior
5+ years

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Senior Engineer responsible for reliability test flow development, test planning, DPM reduction, root cause analysis, process conversion recommendations, risk management, project management, AI strategy for reliability, and applied machine learning for reliability datasets.

Responsibilities

Define and develop reliability stress, test flows and test plans
Work closely with Global Quality team to define qualification plan and manage execution
Drive down and achieve Extrinsic and Intrinsic Reliability through optimized manufacturing test flows
Debug and identify root cause and failures in reliability tests by EFA and PFA
Provide recommendations to fab teams for new process conversions

Requirements

Bachelor's or Master's degree in Electrical and Electronics Engineering or a related field

Skills

Python JMP CMOS technology DRAM architecture device physics data analysis statistics

Engineer, HIG-HBM Product System & Engineering (Media Health Manufacturing)

Micron Technology · Posted Nov 6, 2026

Open

Singapore, Singapore

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Key technical contributor within the High Bandwidth Memory (HBM) Product Engineering – Media Health team, responsible for driving Media Health manufacturing execution for Micron’s next‑generation HBM products, including DRAM die, interface die, and stacked HBM solutions.

Responsibilities

Optimized Test Coverage
Product Development and Validation
Support for New Product Design Validation
Yield Improvement and Cost Reduction
Root Cause and Resolution of Manufacturing Test Flow Issue, Qual and RMA Device Issues

Requirements

Bachelor’s or Master’s degree in Electrical and Electronics Engineering or a related field

Skills

semiconductor devices circuit design product validation CMOS technology DRAM architecture device physics data analysis statistics

Engineer, HIG-HBM Product System & Engineering (Media Health Manufacturing)

Micron Technology · Posted Nov 6, 2026

Open

Singapore, Singapore
On-site
Full-time · Associate

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Key technical contributor driving Media Health manufacturing execution for Micron’s next-generation HBM products, including DRAM die, interface die, and stacked HBM solutions. Focused on Quality, Cost, Cycle Time, and Scale.

Responsibilities

Ensuring optimized test coverage on all current and future HIG HBM design architectures and process nodes.
Developing, validating, characterizing, and qualifying next-generation HBM products.
Supporting design verification and in-depth circuit analysis of new products using CAD tools and Verilog simulations.
Improving manufacturing test yields (DRAM, Interface, and Stacked Die).
Reducing test time and resolving yield-related issues.

Requirements

Bachelor’s or Master’s degree in Electrical and Electronics Engineering or a related field

Skills

semiconductor devices circuit design product validation CMOS technology DRAM architecture device physics

IC Design Engineer

Nexperia · Posted Nov 5, 2026

Open

Nijmegen, Gelderland, Netherlands
Full-time · Entry
0+ years

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Develop and release integrated circuit products in logic and switch families, managing design, verification, and layout using industry-standard EDA tools.

Responsibilities

Develop and release products combining integrated circuits and plastic packages
Contribute to cross‑functional teams during study, concept, design, validation, and qualification phases
Drive chip design, specifications setting, and verification
Own top‑level layout fit for required packages
Design integrated circuits in 0.5um to 0.18um CMOS and BCD wafer processes

Requirements

Master’s degree in electrical engineering

Skills

CMOS IC design analog IC design tools Cadence Synopsys EDA tools simulations semiconductor device physics

Senior IC Design Engineer

Nexperia · Posted Nov 5, 2026

Open

Nijmegen, Gelderland, Netherlands
On-site
Full-time · Senior
3+ years

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Develop and release products consisting of integrated circuits and plastic packages using CMOS or BCD technology and analog IC design tools.

Responsibilities

Develop and release products, which are combinations of integrated circuits and plastic packages
Act as technical lead of a cross-functional team of design engineering, product engineering, test engineering and product quality engineering
Drive full-chip design, product specifications setting and verification while having ownership of top-level layout fit
Design integrated circuits in 0.5um to 0.18um feature size CMOS and BCD wafer processes
Develop products in a wide range of plastic packages with Cu-wire bond wiring

Requirements

Master’s degree in electrical engineering

Skills

CMOS technology BCD technology IC design analog IC design tools Cadence Synopsys

ASIC Analog Designer

Bosch Group · Posted Nov 5, 2026

Open

München, Bavaria, Germany
5+ years

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Design and validate analog circuits for MEMS consumer sensor ASICs at the Munich ASIC Development Center.

Responsibilities

Implement challenging blocks and mixed-signal sensor systems ready for high-volume production
Translate complex design requirements into robust architectures, block specifications and circuit solutions
Collaborate closely on layout and production test development
Take ownership of product validation and assess characterization and qualification results

Requirements

Master’s degree in Electrical Engineering, Computer Science, Mathematics or comparable qualifications
PhD in Electrical Engineering, Computer Science, Mathematics or comparable qualifications

Skills

Analog IC design System level architecture of sensor front-end CMOS technology EDA Software tools for IC design and system level modeling EDA Software

Power Engineer

Apple · Posted Nov 5, 2026

Open

Cupertino, California, United States +1 more
On-site
$208K–$225K per year
2+ years

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Model power dissipation and power delivery for Apple’s silicon and IPs, establish voltage-frequency design points, and collaborate with technology, validation, and product engineering teams.

Locations (2)

Cupertino, California, United States
United States

Compensation

base pay range for this role is between $207,673 - $225,300/yr

Responsibilities

Model power dissipation and power delivery
Establish voltages for DVFM states of IPs
Model power dissipation for customer use-cases
Interact with Technology, Silicon Validation, and Product Engineering teams
Establish voltage-frequency design points pre- and post-silicon

Requirements

Master’s in Electrical Engineering
Master’s in Computer Engineering
Master’s in Computer Science

Skills

VLSI design flow

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