- Cupertino, California, United States
- On-site
- Full-time
- $150K–$225K per year
- 1+ years
Review specifications of Mixed Signal Blocks, develop verification plans, testbenches, and scripts to validate designs.
Compensation
The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.
Responsibilities
- Review specifications of Mixed Signal Blocks
- Define and execute verification plans
- Develop top/block level Mixed Signal and Digital testbenches
- Generate directed/ constrained-random tests in a UVM framework
- Develop checkers/assertions in System Verilog
Requirements
- Bachelor’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or related field