Referso Jobs

Senior Firmware Engineer

Renesas Electronics · Posted Nov 9, 2026

Open

Austin, Texas, United States
Senior

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Senior Firmware Engineer

Renesas Electronics · Posted Nov 9, 2026

Open

Austin, Texas, United States
Senior

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Senior Engineer (Level 1)- Emulation

Arrow Electronics, Inc. · Posted Oct 15, 2025

Open

Bangalore, Karnataka, India
Full-time · Senior
5+ years

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Responsibilities

Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning.
Experience with Verilog, VHDL design Knowledge
Experience with C/C++, DPI and System Verilog add on.
Experience writing scripts using any languages (Perl, Python, Makefile )
Experience with waveform debug tools, Verdi/SimVision.

Requirements

Bachelor's degree

Skills

Emulation Verilog VHDL C/C++DPI System Verilog Perl Python Makefile waveform debug tools

Design Verification

Apple · Posted Nov 5, 2026

Open

Cupertino, California, United States
On-site
Full-time
$150K–$225K per year
1+ years

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Review specifications of Mixed Signal Blocks, develop verification plans, testbenches, and scripts to validate designs.

Compensation

The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Responsibilities

Review specifications of Mixed Signal Blocks
Define and execute verification plans
Develop top/block level Mixed Signal and Digital testbenches
Generate directed/ constrained-random tests in a UVM framework
Develop checkers/assertions in System Verilog

Requirements

Bachelor’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or related field

Skills

Verilog System Verilog UVM Python Perl Cadence Virtuoso Xcelium

Senior Staff Verification Engineer For Worldguard

SiFive · Posted Jun 30, 2026

Open

Bengaluru, Karnataka, India
Senior
10+ years

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Senior Staff Verification Engineer

Responsibilities

Analyze architectural specifications to define verification strategies and create comprehensive test plans
Design and implement scalable, reusable, and constrained-random verification environments using SystemVerilog and UVM
Write complex sequences and constrained-random tests to stress-test the IP across corner cases
Perform deep-dive root cause analysis on RTL design failures and testbench issues using waveform viewers
Define and track functional and code coverage metrics and write cover groups and cover points

Requirements

Bachelor’s in Engineering
Master’s in Engineering
Nice to have: Python scripting

Skills

System Verilog UVM OVM VMM Python Perl C/C++

Senior Firmware Engineer

Senior Firmware Engineer

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Senior Engineer (Level 1)- Emulation

Responsibilities

Requirements

Skills

Design Verification

Compensation

Responsibilities

Requirements

Skills

Senior Staff Verification Engineer For Worldguard

Responsibilities

Requirements

Skills

Benefits

Simvision jobs

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Requirements

Skills

Benefits

Responsibilities

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Skills

Compensation

Responsibilities

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Skills

Responsibilities

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