Lead physical design engineering for complex digital logic blocks, driving placement, routing, timing, and power optimization.
The base pay range for this role is between $216,200 - $324,800/yr
- Conduct floor planning, pin assignments, macro placement and evaluation of logic
- Perform clock tree synthesis, optimization, routing and post-route optimization
- Complete netlist to GDS2 implementation for partitions
- Execute static timing analysis and power analysis
- Perform formal checking and sign off
- Bachelor's degree or foreign equivalent in Electronic Engineering, Electrical Engineering, Computer Engineering
- Comprehensive medical and dental coverage
- Retirement benefits
- Discounted products and free services
- Tuition reimbursement for formal education
- Discretionary restricted stock unit awards
