- Cupertino, California, United States +2 more
- On-site
- Full-time · Senior
- $249K–$349K per year
- 7+ years
Design and develop FPGAs, digital ASICs, and/or mixed-signal ASICs for space-based communication systems.
Locations (3)
- Cupertino, California, United States
- San Diego, California, United States
- Austin, Texas, United States
Compensation
Base Pay Range for: CA applicants is $249,235.00 - $348,928.65
Responsibilities
- Design and develop FPGAs, digital ASICs, and/or mixed-signal ASICs
- Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog)
- Develop verification methodologies and test benches for block and system-level verification
- Create and execute test plans, develop test harnesses, and implement coverage models
- Conduct timing analysis, noise analysis, and other signoff checks