Senior technical leader in DTCO to define and drive co-optimization of Intel Foundry's next-generation process technologies for analog, mixed-signal, and custom design.
Locations (2)
Hillsboro, Oregon, United States
Santa Clara, California, United States
Compensation
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
Responsibilities
Lead AMS DTCO for future Intel Foundry nodes: evaluate device architecture, front-end and back-end design rules, metal stack, and patterning choices against analog, mixed-signal, and custom-design requirements.
Run a closed-loop DTCO process: sense issues from designers, partners, and test chips; prioritize by PPA and productivity impact; drive rule, PDK, or flow changes; and validate the result on silicon and in design.
Quantify technology impact on circuits through layout studies, parasitic-aware benchmarking, and area and performance scaling analysis of representative AMS building blocks.
Define and drive design-rule and PDK requirements with process, design-rule, OPC, and quality and reliability teams, including high-voltage device support, density and fill rules, metal width and spacing options, and layout-dependent effects.
Partner with EDA vendors on node enablement for custom and AMS flows: custom layout, analog placement and routing, physical verification, fill, and extraction; translate tool and flow feedback into technology decisions.
Applications Engineering, Sr EngineerNewSynopsys · US