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ASIC Digital Design, Staff Engineer

Synopsys · Posted Oct 16, 2026

Staff Engineer focused on verifying advanced Ethernet and PCIe SERDES IP using AMS co-simulation, UVM-based testbenches and automation.

Define and execute verification test plans for Ethernet and PCIe SERDES IP, tracking coverage metrics and ensuring completeness across functional, analog, and mixed-signal scenarios
Build and maintain UVM-based SystemVerilog testbenches integrated with AMS co-simulation flows, combining RTL, behavioral models, and transistor-level netlists into unified verification platforms
Verify SERDES subsystems including TX/RX datapaths, equalization algorithms, CDR loops, PLL locking behavior, and analog-digital interface interactions across process corners and operating conditions
Debug simulation failures that span analog, digital, and mixed-signal domains using tools like HSPICE, XA, CustomSim, and VCS
Perform design reliability checks including electromigration, IR drop analysis, and device-level stress evaluations to ensure robustness in production silicon