SiTime is seeking a seasoned Principal DFT Engineer to lead the DFT architecture, implementation, verification, and signoff of complex digital blocks and subsystems, taking end-to-end ownership from architecture through specification through to silicon bring-up and manufacturing support.
Compensation
$160,920—$230,140 USD
Responsibilities
Serve as the technical focal point for DFT, leading architecture, implementation, verification, and signoff reviews, and establishing reusable methodologies across multiple programs.
Define DFT architecture and specifications, including scan architecture, compression, test access, clocking, test modes, core wrapping, and hierarchical DFT strategy.
Implement and validate digital DFT structures, including scan insertion, OCC insertion, advanced compression architectures such as EDT and LPCT, and core wrapping.
Develop and continuously improve automated, reproducible DFT implementation, verification, ATPG, and signoff flows to increase productivity, reduce execution risk, and ensure consistent test quality across multiple programs.
Own ATPG generation, pattern validation, fault analysis, and coverage closure, identifying and resolving testability limitations to achieve product coverage and quality targets.
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