Lead the development and execution of corporate-level strategies for high-speed signaling technologies across advanced semiconductor packaging, sockets, and connectors.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 320,000 USD – 488,750 USD.
Responsibilities
Lead the development and execution of corporate-level strategies for high-speed signaling technologies across advanced semiconductor packaging, sockets, and connectors.
Oversee technical direction and implementation for next-gen products ranging from ultra-mobile to high-performance AI and HPC platforms.
Architect and deliver state-of-the-art interconnect and packaging solutions for standards such as UCIe, HBM, DDR, PCIe, and industry-leading SerDes (224G/448G).
Enable advanced packaging technology solutions for co-packaged optics, stacked die, chiplet-based architectures and IVR solutions.
Development of modeling and characterization flows, flow automations, design for high volume manufacturing techniques.
Lead the development and execution of corporate-level strategies for high-speed signaling technologies across advanced semiconductor packaging, sockets, and connectors.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 320,000 USD – 488,750 USD.
Responsibilities
Lead the development and execution of corporate-level strategies for high-speed signaling technologies across advanced semiconductor packaging, sockets, and connectors.
Oversee technical direction and implementation for next-gen products ranging from ultra-mobile to high-performance AI and HPC platforms.
Architect and deliver state-of-the-art interconnect and packaging solutions for standards such as UCIe, HBM, DDR, PCIe, and industry-leading SerDes (224G/448G).
Enable advanced packaging technology solutions for co-packaged optics, stacked die, chiplet-based architectures and IVR solutions.
Development of modeling and characterization flows, flow automations, design for high volume manufacturing techniques.
An experienced ASIC Package Engineer focused on advanced packaging development, process integration, and designing custom silicons for infrastructure/AI/ML and networking applications.
Locations (2)
Hsinchu, Taiwan, Taiwan
Taipei, Taiwan, Taiwan
Responsibilities
Perform package design for AI/ML and networking applications custom Si with single-chip/multi-chip and SiP/module packaging
Design feasibility studies and analyses to ensure good manufacturing at ODM
Lead development of disruptive advanced packaging technologies from concept to product, including test vehicle definition and building with ecosystem partners
Work with internal Si, architecture and system teams, and externally with engaged partners, ODM, design houses and OSAT companies
Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration
