Architect, implement, and optimize core services spanning on-premises arrays and cloud deployments to deliver seamless storage experiences to enterprises globally, focusing on FlashBlade platform architecture.
Locations (3)
Bengaluru, Karnataka, India
Silicon Valley, United States
Prague, Prague, Czech Republic
Responsibilities
Own the platform software architecture for New Product Introduction (NPI) programs across FlashArray and FlashBlade
Define and drive the platform security architecture (PRoT, UEFI Secure Boot, TPM, measured boot, etc.)
Extend the secure boot chain of trust across firmware, bootloaders, kernel, Purity software and devices
Drive the post-quantum cryptography (PQC) readiness roadmap
Architect secure, resilient firmware update and lifecycle flows
Requirements
Bachelor’s or higher in Computer Science, Computer Engineering or Electrical Engineering
Nice to have: PQC algorithms and migration
Nice to have: Common Criteria / FIPS certification
Own the multi-year roadmap and commercial strategy for our Trusted Control/Compute Unit (TCU) SoCs, Platform Intelligence Controllers (PIC), and DC-SCM modules—driving flagship products from initial definition to silicon bring-up.
Compensation
$200,000–$250,000 base salary plus equity, bonus, and benefits.
Responsibilities
Author flagship PRDs and MRDs, translating customer workloads into granular hardware, firmware, and on-chip AI specifications
Own the multi-generational TCU/PIC roadmap, pricing, and P&L
Mentor and scale a lean team of PMs
Lead technical and commercial engagements with CSPs, Tier-1 OEMs/ODMs, and silicon partners (Arm, NVIDIA, x86) to secure design-wins and shape OCP standards
Partner daily with Silicon, Firmware, and AI Engineering on Performance-Power-Area (PPA), Dynamic Voltage & Frequency Scaling (DVFS), Hardware Root of Trust (RoT), and out-of-band telemetry
Requirements
BS in EE, CE, CS, or related technical field
Nice to have: AI-driven hardware telemetry
Nice to have: dynamic power/thermal management (DVFS)
As a Senior Hardware Engineer – FPGA & Platform Security on SPARC, you will help define and build the hardware root of trust that protects Azure’s fleet, from silicon and FPGA prototypes through firmware, BMC, and datacenter deployment.
Locations (2)
Redmond, Washington, United States
Mountain View, California, United States
Compensation
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Define requirements, specifications, and interface definitions for server platform features, including trust and integrity capabilities such as secure boot, attestation, and firmware recovery.
Lead bring-up of new server, SoC, and FPGA-based platforms, from first power-on through firmware, BMC, and OS boot, and work with hardware and firmware partners to resolve issues quickly.
Set up, maintain, and evolve lab infrastructure, including racks, networking, power, debug tooling, and remote management access, so engineers can validate new platforms efficiently.
Lead design and development of security features for SONiC and Linux-based network operating systems, drive security architecture, and provide technical leadership.
Locations (2)
Chennai, Tamil Nadu, India
Bangalore, Karnataka, India
Responsibilities
Lead design and development of security features for SONiC and Linux-based network operating systems
Drive security architecture for routing, switching, EVPN-VXLAN, AI fabrics, and platform security technologies
Champion Secure Development Lifecycle practices
Partner with product security, platform, architecture, and quality teams to identify risks and ensure secure product delivery
Provide technical leadership and mentorship while leveraging AI-assisted development and testing tools
Requirements
Bachelor's or Master's degree in Computer Science, Computer Engineering, or a related field
Lead design and development of security features for SONiC and Linux-based network operating systems, drive security architecture, champion SDL practices, partner with product security and platform teams, provide technical leadership and mentorship.
Responsibilities
Lead the design and development of security features for SONiC and Linux-based network operating systems across data, control, and management planes
Drive security architecture for routing, switching, EVPN-VXLAN, AI fabrics, and platform security technologies including secure boot, firmware validation, container security, and hardware root of trust
Champion Secure Development Lifecycle (SDL) practices, including threat modeling, secure design reviews, code reviews, and security compliance automation
Partner with product security, platform, architecture, and quality teams to identify risks, resolve complex issues, and ensure secure product delivery
Provide technical leadership and mentorship while leveraging AI-assisted development and testing tools to improve engineering productivity and software quality
Requirements
Bachelor's or Master's degree in Computer Science, Computer Engineering, or a related field
Own the hardware security architecture for Positron AI’s AI accelerator platform, ensuring protection of customer models, user data, firmware, intellectual property, and secure operation throughout the product lifecycle.
Locations (2)
United States
Canada
Compensation
The base salary range for this role is $200,000 – $300,000.
Responsibilities
Define the overall silicon security architecture
Own secure boot, hardware root of trust, chain of trust, authenticated firmware, and measured boot
Own secure debug, secure manufacturing, fuse programming, key provisioning, and device identity
Own key ladders, anti-rollback protections, JTAG security, scan access control, and lifecycle states
Protect customer models and weights through weight encryption and weight authentication
Prototype and integrate root-of-trust and HSM capabilities (for example, Caliptra) on FPGA and emulation platforms, and develop validation plans that cover normal, fault, and recovery scenarios.
Build diagnostics, telemetry, and automated recovery tools that help fleet hardware detect problems, report its health, and return to a known-good state with minimal manual intervention.
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Hardware Security ArchitectPositron Corporation · Remote, US+1 more