- Hyderabad, Telangana, India
- Full-time · Senior
Senior Design Verification Engineer
Responsibilities
- Develop and execute comprehensive verification plans for SOC and IP designs
- Utilize Verilog and System Verilog to create and maintain testbenches and verification environments
- Implement UVM-based verification methodologies to enhance the efficiency and effectiveness of the verification process
- Collaborate with design engineers to understand specifications and requirements for various protocols, including AXI, APB, CHI, and USB
- Write and maintain verification code in C/C++ to support advanced verification tasks
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field