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$186K–$345K
Full-time · Senior
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RTL Design Engineer for Mixed-Signal IPs responsible for developing, integrating, and verifying digital RTL blocks within mixed-signal subsystems.
Lead project activities and mentor less experienced engineers; architect, specify, implement, simulate, and benchmark MCU and DSP systems and hardware accelerators; contribute to design methodology and flow improvements; consult product integration teams; participate in verification and FPGA prototyping; coordinate SDK development with software team.
Cadence Design Systems · Posted Nov 4, 2026
Lead technical architecture for Cadence interface IP integration in customer SoCs, driving pre‑ and post‑sales engagements and product definition.
The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Senior Design Verification Engineer