- Full-time · Staff
- 5+ years
Staff Engineer to lead layout development for cutting-edge DDR, HBM, and UCIe PHY IP across 7nm and below process nodes including FinFET and GAA technologies, while mentoring juniors and collaborating with cross-functional teams.
Responsibilities
- Lead layout development for cutting edge DDR, HBM, and UCIe PHY IP across 7nm and below process nodes including FinFET and GAA technologies
- Own floorplanning, layout matching, ESD design, latch-up mitigation, and DFM compliance for analog and mixed-signal blocks
- Drive layout reviews, quality checks, PERC and EMIR analysis, and release processes that meet both internal standards and customer requirements
- Mentor junior layout engineers through hands-on technical leadership, teaching them how to solve real problems in deep submicron design
- Collaborate with cross-functional teams including analog designers, verification engineers, and foundry partners to meet project timelines
Requirements
- BTech
- MTech
- Electronics Engineering
- VLSI
- Nice to have: PHY level customer requirements