- Austin, Texas, United States
- On-site
- Full-time · Senior
- 8+ years
Own hardware safety analysis for processor IP configurations and perform SoC-level safety analysis for Custom Silicon programs, contributing to safety architecture for ARC MIPS processor IP certified to ISO 26262.
Compensation
The exact Salary will be determined based on qualifications, experience and location.
Responsibilities
- Own hardware safety analysis for processor IP configurations: FMEDA, DFMEA, DFA and FTA, through to external assessment
- Perform SoC-level safety analysis for Custom Silicon programs: integration of safety elements, system-level FMEDA, and the safety concept at the SoC boundary
- Analyze dependent failures and freedom from interference across IP boundaries within an SoC
- Derive and track safety metrics (SPFM, LFM, PMHF) and drive diagnostic coverage improvement together with the STL and verification teams
- Define and review safety mechanisms at RTL level — ECC, parity, lockstep, register protection, watchdog — and verify they meet the claimed diagnostic coverage
Requirements
- Master's or Bachelor's degree in Electrical/Electronic Engineering, Computer Engineering or a related field
- Nice to have: ISO 26262 certification or formal training
- Nice to have: Safety Element out of Context (SEooC) supplier experience
- Nice to have: Fault simulation tooling (VC Z01X or equivalent)
- Nice to have: Scripting and automation (Python, TCL)