- Bay Area, California, United States
- Senior
- 8–12 years
Seeking an RTL2PD Design Engineer with strong experience in timing constraints, RTL synthesis, and static timing analysis for ASIC multi-node designs.
Responsibilities
- RTL Synthesis
- Constraint writing
- validation
- Static timing Analysis
- Writing Scripts/Modying scripts for RTL synthesis, SDC creation, STA
Requirements
- Nice to have: 16nm experience
- Nice to have: 7nm experience