The Integration Design Engineer will be part of the Silicon Integration Team, responsible for integrating different IPs to build the chip using both custom and digital design flows.
Responsibilities
Integrate different IPs to build the fullchip.
Deliver all corresponding models, views, and collaterals to functional teams.
Complete all required checks and simulations for sign-off.
Collaborate with Architecture, SW, IP Design, and Physical Design Teams to generate fullchip logical floorplan.
Generate fullchip behavioral model by integrating various IP models.
An integration design engineering role focused on Custom and Digital Design Implementation, specifically using Verilog and System Verilog for programmable logic solutions.
Responsibilities
Custom Design Flow implementation
Semiconductor principles and transistor-level analysis
Characterization, performance, and power simulations
RTL coding and verification
Lint Check, Elaboration/Compilation, Synthesis, Equivalence Check, SDC, and STA
Requirements
BS or MS in Electronics Engineering
BS or MS in Computer Engineering
BS or MS in Electrical Engineering
Nice to have: FPGA/CPLD design and integration
Nice to have: IP and Fullchip functional verification
The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII.
Compensation
The base salary range is $140,000 - $156,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.
Responsibilities
floor-planning
auto place and route
static timing analysis
eco implementation
signal integrity analysis
Requirements
BS/MS in EE/computer science or equivalent experience
Lead technical engagements and drive advanced design solutions for semiconductor customers as a senior Application Engineer.
Compensation
The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Responsibilities
Lead technical engagements with customers and partners to achieve best-in-class PPA
Guide adoption of Cadence’s digital implementation, signoff technologies and AgenticAI features across advanced nodes
Partner with R&D and Product Engineering to influence tool enhancements
Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for Synthesis, P&R, STA, IR Drop, and power/timing closure
Represent Cadence at industry forums, author technical papers, and deliver keynote presentations
The Engineer will lead Broadcom's design methodology for 5nm and lower technology silicon, focusing on floor-planning, placement, CTS, route, and physical verification.
Responsibilities
Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
Maintain deep functional knowledge of P&R flows
Implement timing and functional ECO
P&R, Extraction, Physical verification, work towards STA closure
Build automation flows wherever needed/adapt to existing flows for re-use
Convert RTL designs into netlists using industry-standard RTL synthesis tools and optimize power, performance, and area.
Responsibilities
Convert RTL designs into netlists using industry-standard RTL synthesis tools
Optimize power, performance, and area by experimenting with synthesis recipes and enhancing existing synthesis methodologies
Understand RTL code written in Verilog and SystemVerilog languages, correlate it to gate-level circuits, and guide the development of optimal RTL solutions
Perform Clock and Reset Domain Crossing (CDC,RDC) checks to ensure the design's robustness against metastability-related problems and lint checks
Perform logical equivalence checks to ensure correctness of the generated netlist and support ECO generation activities
Requirements
Master's degree in Electrical and Computer Engineering, Electrical Engineering, or a related field
Senior ASIC Engineer responsible for DFT design, verification, and integration.
Responsibilities
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products
Requirements
Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
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