Lead the design and implementation of an ultra-low-latency electronic trading platform targeting microsecond and sub-microsecond latencies.
The Expected Salary Range For The Above Position Is $210,000 - $275,000 Depending On Factors Including But Not Limited To The Candidate’s Experience, Skills, Registration Status; Market Conditions; And Business Needs.
- Design the foundational messaging layer and evaluate trade-offs between FIX and Simple Binary Encoding
- Architect FPGA-based acceleration for latency-critical paths including market data feed parsing and order routing
- Bypass the kernel network stack using DPDK, Open Onload or similar frameworks
- Design deterministic, replayable event streams with minimal latency overhead
- Design market data ingestion layer targeting microsecond-scale processing
- Nice to have: Experience with market data feed handlers and direct exchange connectivity
- Nice to have: Track record of building end-to-end ultra-low-latency systems from architecture through production
- Nice to have: Familiarity with order entry normalization frameworks
- Nice to have: Experience with kernel-bypass networking (DPDK, Open Onload, etc.)
- Nice to have: Experience designing systems that pass regulatory audits or compliance reviews