Design front‑end RF signal‑chain circuits and assemblies for space vehicle communication and signal analysis systems.
Compensation
Compensation: Base salary range is $100,000-130,000/year, depending on qualifications. SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan. In addition to base salary, employees are eligible for a year-end bonus.
Responsibilities
Design front‑end RF signal‑chain circuits and assemblies for space vehicle communication and signal analysis systems using filters, amplifiers, mixers, couplers, impedance matching networks, and related components
Design stable, low‑phase noise oscillators and distribution networks
Design RF digitizer circuits and assemblies using multi‑GSPS ADC/DAC components
Cooperate with project teams over the course of RF system development to establish technical requirements, perform system trade studies, conduct design reviews, and track delivery schedule
Collaborate with RF group members and other SEAKR engineers to ensure that all multidisciplinary requirements can be satisfied in the assigned designs
Requirements
BSEE or equivalent university degree
Nice to have: Sampling and signal processing in digital RF systems
The HSIO Validation Engineer will own the characterization and qualification of high-speed I/Os—such as PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet—on brand-new silicon serving datacenter, AI, and client markets.
Responsibilities
Own end-to-end characterization and validation of high-speed IO — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet — from silicon die through package and board, on NVIDIA GPUs, CPUs, and SoCs.
Develop and execute validation test plans for silicon and SoC-level HSIO features — bring-up, corner qualification, stress, productization, and structured DOE across PVT, board, cable/connector, thermal, and firmware variables.
Drive power characterization and optimization across IO interconnects under workload-representative stimuli.
Drive systematic root-cause analysis for complex HSIO bugs — isolating contributions across silicon, package, board, firmware, and driver.
Assess manufacturing and yield implications of HSIO margin distributions.
Signal Integrity Engineer III – R&D Networking Platforms
Locations (2)
Sunnyvale, California, United States
Roseville, California, United States
Compensation
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 109,500 - 220,500 in California
Responsibilities
Support the design and validation of signal and power integrity solutions for system-level high-speed interfaces, power distribution networks (PDN), high-precision timing, and general-purpose I/O.
Develop robust, cost-effective SI/PI solutions through analysis, simulation, design-of-experiments, and lab correlation using modern tools and methodologies.
Perform interconnect and PDN modelling, SI/PI simulations, and analysis to help ensure designs meet performance, reliability, and industry specifications.
Contribute to PCB stack-ups, design rules, and constraints, and participate in design reviews to ensure compliance with SI/PI best practices and standards.
Lead end‑to‑end characterization and validation of high‑speed I/O on NVIDIA silicon.
Responsibilities
Own end‑to‑end characterization and validation of high‑speed IO from silicon die through package and board on NVIDIA GPUs, CPUs, and SoCs.
Develop and execute validation test plans for silicon and SoC‑level HSIO features, including corner qualification, stress, productization, and structured DOE across PVT, board, cable/connector, thermal, and firmware variables.
Drive power characterization and optimization across IO interconnects under workload‑representative stimuli, analyze trade‑offs across V/F, lane config, and protocol state, and feed back into design, firmware, and binning.
Drive systematic root‑cause analysis for complex HSIO bugs, isolating contributions across silicon, package, board, firmware, and driver, with platform/thermal/mechanical partners when system context matters.
Assess manufacturing and yield implications of HSIO margin distributions, identify gaps in scaling from chip to product, and feed back into binning and design.
Requirements
BS or MS in Electrical or Computer Engineering (or equivalent)
The Engineering Manager, Photonics Hardware Validation owns the characterization, verification, validation, performance classification, and failure analysis of electro-optical subassemblies integrated with custom photonic integrated circuits (PICs). The role focuses on the validation of single-photon sources and detectors, leading validation strategy and execution from proof-of-concept through early hardware bring-up through qualification and manufacturing readiness.
The estimated annual base salary range for this role is: Zone 1: $201,400—$236,600 USD, Zone 2: $181,200—$212,900 USD, Zone 3: $161,100—$189,300 USD, Zone 4: $140,900—$165,600 USD
Responsibilities
Lead, hire, and grow a photonics hardware validation team; define technical ownership, priorities, staffing plans, and career development opportunities.
Own comprehensive characterization, verification, and validation plans for photonic modules and electro-optical subassemblies, from initial hardware bring-up through qualification and manufacturing transfer.
Establish repeatable measurement methods, calibration practices, uncertainty analysis, experimental designs, data-review processes, and configuration-controlled test documentation.
Drive cross-functional debugging, failure analysis, and root-cause investigations; verify corrective actions and clearly communicate residual risks and recommended next steps.
Review integrated optical, electrical, firmware, software, packaging, and thermal designs; identify critical measurements and influence design-for-testability and validation access.
Requirements
Bachelor’s degree in electrical engineering, physics, optics, photonics, or a related field
Master’s degree or PhD in a relevant technical discipline (preferred)
Nice to have: single-photon detection
Nice to have: low-noise RF readout chains
Nice to have: characterization of low-level optical and electrical signals
Manager, Photonics Hardware Validation EngineeringPsiQuantum · Remote, US+11 more