- Sunnyvale, California, United States
- On-site
- Full-time · Mid
- $163K–$236K per year
- 5+ years
Design and verify advanced DFT methodologies for TPU SoCs
Compensation
US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Responsibilities
- Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
- Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
- Develop diagnostic databases, software and hardware for logic and memory fail debug.
- Design and implement system level test strategy.
- Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science