As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation.
Compensation
The base salary range for this role is $200,000 – $300,000.
Responsibilities
Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features.
Integrate DFT IP into internally developed RTL, and evaluate and integrate DFT capabilities from third-party IP providers.
Work directly in RTL, synthesis, and DFT tool flows.
Develop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification.
Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.
Requirements
BS, MS, or PhD in Electrical Engineering or Computer Engineering
Deliver end-to-end DFT solutions for customer designs ranging from mid-complexity ASICs to massive multi-IP SoCs, covering architecture planning, scan insertion, ATPG pattern generation, MBIST integration, and silicon bring-up support.
Compensation
Your recruiter will provide more details about the salary range and benefits during the hiring process.
Responsibilities
Deliver end-to-end DFT solutions for customer designs ranging from mid-complexity ASICs to massive multi-IP SoCs, covering architecture planning, scan insertion, ATPG pattern generation, MBIST integration, and silicon bring-up support
Provide technical guidance during early design phases, helping customers budget for test, plan DFT architectures, and avoid costly mistakes before RTL freeze
Implement and validate scan, MBIST, and IEEE 1687 test solutions, running simulations, debugging failures, and ensuring coverage targets are met
Join customer design reviews to understand their flows, identify gaps or risks, and recommend improvements grounded in real-world test methodology
Prototype and validate next-generation DFT techniques in collaboration with solution architects, turning experimental ideas into production-ready workflows
Requirements
Bachelor's degree with 7+ years of hands-on experience
Master's degree with 5+ years
Nice to have: MBIST in automotive or safety-critical design environments
An ASIC Design for Test Engineer role focused on Design-for-Test (DFT) within the Silicon One team creating hardware platforms.
Compensation
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, and/or training.
Responsibilities
Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
Create and enhance automation scripts to improve implementation robustness and efficiency.
Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog.
Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.
Requirements
Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months)
