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Define and lead the global NAND DFT vision, strategy, and technical roadmap
Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off
Partner with Design and Project teams to embed testability early and resolve performance, power, area, reliability, cost, and schedule trade-offs
Drive reusable methodologies, automation, and DFT and design-for-debug innovation
Build, develop, and inspire a high-performing global DFT organization

Requirements

M.S. or Ph.D. in Electrical Engineering, Electronics, Computer Engineering, or a related field
Nice to have: NAND Flash
Nice to have: non-volatile memory technologies
Nice to have: memory test algorithms
Nice to have: embedded self-test/diagnostics

Skills

Semiconductor design DFT product test

Design / DFT Director (NVE Engineering)

Micron Technology · Posted Nov 9, 2026

Open

Avezzano, Aquila, Italy
On-site
Full-time · Director

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Seeking an expert and innovative Director of NAND Design for Test (DFT) to lead the global DFT strategy, architecture, and execution for advanced NAND Flash products at Micron Semiconductor Italia.

Responsibilities

Define and lead the global NAND DFT vision, strategy, and technical roadmap across product programs and technology generations.
Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off from early product definition through tape-out.
Partner with Design and Project teams to embed testability early and resolve performance, power, area, reliability, cost, and schedule trade-offs.
Drive reusable methodologies, automation, and DFT and design-for-debug innovation.
Build, develop, and inspire a high-performing global DFT organization.

Requirements

M.S. or Ph.D. in Electrical Engineering
Electronics
Computer Engineering, or a related field
Nice to have: NAND Flash experience
Nice to have: non-volatile memory technologies

Skills

semiconductor design DFT product test silicon validation

MTS Silicon Design Engineer

Advanced Micro Devices, Inc · Posted Nov 6, 2026

Open

San Jose, California, United States
3+ years

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Design, develop, and test electronic components and systems for semiconductor manufacturing, including ASIC design and verification.

Responsibilities

Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing
Oversee definition, design, verification, and/or documentation for ASIC development
Determine architecture design, logic design, and/or system simulation
Define module interfaces/formats for simulation
Lead the development of multidimensional designs involving the layout of complex integrated circuits

Requirements

Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field
Bachelor’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field with five years of progressive, post-baccalaureate experience

Skills

Design of digital circuits and components using Verilog or SystemVerilog Debugging in digital and mixed-signal simulation environment Multi-clock domain designs

Analog Senior or Staff Design Engineer

Micron Technology · Posted Nov 5, 2026

Open

Tokyo, Tokyo, Japan
Senior
2+ years

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Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs, including transistor-level digital, analog, mixed-signal, monitoring, control, and memory-array interface circuits.

Responsibilities

Interpret product specifications and test requirements; define circuit functionality, interfaces, operating limits, controllability, observability, and validation criteria.
Create, review, and optimize schematics, device sizing, bias structures, sensing and monitoring paths, multiplexers relevant to test circuits.
Analyze circuit testability and robustness to ensure compliance with quality, coverage, manufacturability, power, area, and reliability.
Validate custom test circuits using XA simulation, Verilog simulation, and mixed-signal verification environments.
Collaborate closely with layout teams on matching, parasitic sensitivity, shielding, routing, guard rings, device placement, and layout-dependent effects.

Requirements

Electrical Engineering
Electronics Engineering
Computer Engineering
Nice to have: NAND flash memory architecture
Nice to have: Test modes

Skills

Custom/analog circuit design Mixed-signal design

Sr DFT Engineer

NXP Semiconductors · Posted Nov 4, 2026

Open

Hyderabad, Telangana, India
On-site
Full-time · Senior

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Responsible for designing, implementing, and verifying DFT architectures for complex SoCs, working with RTL, physical design, and verification teams.

Responsibilities

Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan)
Develop and integrate scan insertion, test compression, and ATPG patterns
Implement memory BIST and logic BIST strategies
Collaborate with RTL and physical design teams for DFT insertion and timing closure
Perform DFT verification at RTL and gate-level simulations

Requirements

Bachelor’s in Electrical/Electronics Engineering
Master’s in Electrical/Electronics Engineering
Nice to have: SoC level DFT
Nice to have: high-speed interfaces
Nice to have: DFT for mixed-signal blocks

Skills

DFT methodologies Scan MBIST LBIST JTAG ATPG tools UPF/CPF-based low-power DFT

Digital Failure Analysis Engineer

Digital Failure Analysis Engineer

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Design / DFT Director (NVE Engineering)

Compensation

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Design / DFT Director (NVE Engineering)

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MTS Silicon Design Engineer

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Analog Senior or Staff Design Engineer

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Sr DFT Engineer

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Silicon Debug jobs

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