- San Jose, California, United States
- $144K–$230K per year
- 14+ years
Design and implement ASIC DFT solutions, including scan, MBIST, TAP, LBIST, IO, SerDes, and other DFT integration for Broadcom’s SoC products.
Compensation
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
Responsibilities
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Working closely with STA and DI Engineers design closure for test
- Generating, Verifying & Debugging Test vectors before tape release
- Validating & Debugging Test vectors on ATE during the silicon bring up phase
- Assisting with silicon failure analysis, diagnostics & yield improvement efforts
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field