ASIC DFT Engineer
Broadcom · Fort Collins, US· On-site · Full-time · Senior
ASIC DFT Engineer
Broadcom · Fort Collins, US· On-site · Full-time · Senior
ASIC DFT Engineer
Broadcom · Fort Collins, US· On-site · Full-time · Senior
ASIC DFT Engineer
Broadcom · Fort Collins, US· On-site · Full-time · Senior
ASIC DFT Engineer
Broadcom · Fort Collins, US· On-site · Full-time · Senior
ASIC DFT Engineer
Broadcom · San Jose, US· On-site · Full-time · Senior
ASIC DFT Engineer
Broadcom · San Jose, US
ASIC DFT Engineer I
Cisco · San Jose, USFull-time · Entry
DFT Lead Engineer
Broadcom · Austin, US· Senior
DFT Engineer
Broadcom · Austin, US
+10K new in the last hour
Broadcom · Posted Nov 11, 2026
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DFT Engineer for ASIC/Chip level ATPG
The annual base salary range for this position is USD 129,400.00 To USD 207,000.00
Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns Collaborate closely with STA and design integration engineers for timing and design closure Generate, verify, and debug test vectors prior to tapeout release Bachelors in Electrical/Electronic/Computer Engineering Masters Degree in Electrical/Electronic/Computer Engineering Nice to have: In-Field testing solutions Nice to have: ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) DFT architecture and implementation (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6) EDA tools for scan insertion, compression, and ATPG (DFT Compiler, TestKompress, TetraMax, FastScan) Memory and logic BIST strategies, verification, and debug (SRAM, CAM, RF, ROM) Verilog coding Testbench development ATPG pattern generation Simulation Timing constraints/Test-STA Digital/analog circuit design Device physics Silicon manufacturing Synthesis Transistor reliability Root-cause debug Statistical process control Data analysis DFT Compiler TestKompress TetraMax FastScan Python TCL C++ Medical dental and vision plans 401(K) participation including company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP) Broadcom · Posted Nov 11, 2026
DFT Engineer for ASIC/Chip level ATPG
The annual base salary range for this position is USD 129,400.00 To USD 207,000.00
Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns Collaborate closely with STA and design integration engineers for timing and design closure Generate, verify, and debug test vectors prior to tapeout release Bachelors in Electrical/Electronic/Computer Engineering Masters Degree in Electrical/Electronic/Computer Engineering Nice to have: In-Field testing solutions Nice to have: ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) Broadcom · Posted Nov 11, 2026
DFT Engineer for ASIC/Chip level ATPG
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns Collaborate closely with STA and design integration engineers for timing and design closure Generate, verify, and debug test vectors prior to tapeout release Bachelors in Electrical/Electronic/Computer Engineering Masters Degree in Electrical/Electronic/Computer Engineering Nice to have: In-Field testing solutions Nice to have: ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) Broadcom · Posted Nov 11, 2026
DFT Engineer for ASIC/Chip level ATPG
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns Collaborate closely with STA and design integration engineers for timing and design closure Generate, verify, and debug test vectors prior to tapeout release Bachelors in Electrical/Electronic/Computer Engineering Masters Degree in Electrical/Electronic/Computer Engineering Nice to have: In-Field testing solutions Nice to have: ATE silicon bring-up Nice to have: high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) Broadcom · Posted Nov 11, 2026
DFT Engineer for ASIC/Chip level ATPG
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns Collaborate closely with STA and design integration engineers for timing and design closure Generate, verify, and debug test vectors prior to tapeout release Bachelors in Electrical/Electronic/Computer Engineering Masters Degree in Electrical/Electronic/Computer Engineering Nice to have: In-Field testing solutions Nice to have: ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) Broadcom · Posted Nov 9, 2026
The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up, supporting various phases of SoC DFT-related activities for Broadcom APD’s designs.
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration Working closely with STA and DI Engineers design closure for test Generating, Verifying & Debugging Test vectors before tape release Validating & Debugging Test vectors on ATE during the silicon bring up phase Bachelor's degree in Electrical Engineering Master's degree in Electrical Engineering Bachelor's degree in Computer Engineering Master's degree in Computer Engineering Nice to have: Experience working on ATE Broadcom · Posted Nov 9, 2026
Design and implement ASIC DFT solutions, including scan, MBIST, TAP, LBIST, IO, SerDes, and other DFT integration for Broadcom’s SoC products.
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration Working closely with STA and DI Engineers design closure for test Generating, Verifying & Debugging Test vectors before tape release Validating & Debugging Test vectors on ATE during the silicon bring up phase Assisting with silicon failure analysis, diagnostics & yield improvement efforts Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Cisco · Posted Nov 6, 2026
An ASIC Design for Test Engineer role focused on Design-for-Test (DFT) within the Silicon One team creating hardware platforms.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, and/or training.
Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs. Create and enhance automation scripts to improve implementation robustness and efficiency. Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog. Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis. Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months) Nice to have: SystemVerilog Nice to have: logic equivalency checking Nice to have: test-timing validation Nice to have: VLSI circuit physical behaviors Broadcom · Posted Nov 6, 2026
Lead DFT Engineer responsible for DFT programs from specification to production for Broadcom ASIC products.
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
Leading DFT programs from chip level specification to implementation and verification Defining DFT specifications for ASICs Implementing DFT including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration Working closely with STA and DI Engineers for test closure Generating, verifying and debugging test vectors before tape release Bachelor's in Electrical/Electronic/Computer Engineering Master's in Electrical/Electronic/Computer Engineering Broadcom · Posted Nov 6, 2026
Design, implement, and verify DFT programs for Broadcom ASIC products.
The annual base salary range for this position is USD To USD
Understanding Broadcom & customer DFT feature requirements Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration Working closely with STA and DI Engineers design closure for test Generating, Verifying & Debugging Test vectors before tape release Validating & Debugging Test vectors on ATE during the silicon bring up phase Bachelors in Electrical/Electronic/Computer Engineering Masters Degree in Electrical/Electronic/Computer Engineering Medical dental and vision plans 401(K) participation including company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP)
Medical dental and vision plans 401(K) participation including company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP)
Medical dental and vision plans 401(K) participation including company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP)
Medical dental and vision plans 401(K) participation including company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP)
Medical dental vision plans 401(K) with company matching Employee Stock Purchase Program (ESPP)
Medical, dental and vision plans 401(K) participation including company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP) Company paid holidays
medical, dental and vision insurance 401(k) plan Cisco matching contribution paid parental leave short and long-term disability coverage
Medical Dental Vision 401(K) participation with company matching Employee Stock Purchase Program
Medical dental vision plans 401(K) participation company matching
ASIC DFT Engineer ICisco · San Jose, US