A Design/SDC Engineer focused on timing constraints, SDC/STA tools, and seamless physical design closure for next-generation networking chips.
Responsibilities
Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Requirements
Bachelor’s Degree in Electrical or Computer Engineering
Master’s Degree in Electrical or Computer Engineering
Senior PD CAD Equivalency Engineer responsible for formal equivalency flows for Microsoft’s silicon programs.
Compensation
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Own the end-to-end formal equivalency CAD flow, including RTL-to-netlist, netlist-to-netlist, functional ECO, and low-power (UPF-aware) verification, for Microsoft’s silicon programs
Develop, debug, and maintain production flows and automation in Tcl and Python for Synopsys Formality and Cadence Conformal, including handling of complex design classes
Partner with physical design, front-end/synthesis, and signoff teams and with EDA vendors (Synopsys, Cadence) to qualify new tool releases, resolve critical tool issues, and support design teams through tapeout closure
Independently drive technical decisions for the equivalency domain, identify root causes of ambiguous tool behavior, and define clear paths to resolution; mentor and serve as a backup for other engineers in the team
Deliver measurable improvements in flow quality, runtime, and reliability, including regression coverage, documentation, and support turnaround for design teams
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
