- Sunnyvale, California, United States
- On-site
- Full-time · Senior
- $163K–$236K per year
- 8+ years
Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
Compensation
US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Responsibilities
- Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
- Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations.
- Develop timing constraint and verify it for sign-off.
- Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts.
- Own and maintain Primetime STA flows.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
- Nice to have: writing, reviewing and verifying complex Tcl constraints
- Nice to have: extraction of design parameters
- Nice to have: QoR metrics