- Haifa, Haifa District, Israel +1 more
- On-site
- Full-time · Mid
- 2+ years
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
Locations (2)
- Haifa, Haifa District, Israel
- Herzliya, Tel Aviv District, Israel
Responsibilities
- timing sign-off
- STA and sign-off flow development
- ownership of Full chip, IP, and block level timing constraints
- interact with RTL designer to understand design intent and clock structure
- interact with CAD to understand and develop flow
Requirements
- B.Sc / M.Sc in Electrical or Computer Engineering