- Sunnyvale, California, United States
- On-site
- Full-time · Mid
- $116K–$165K per year
Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology for Google's most demanding AI/ML applications, focusing on SoC-level RTL design for data center accelerators.
Compensation
US: $116000 - $165000 (USD) + 15% bonus target + equity + benefits
Responsibilities
- Create and review clock control subsystem's design micro-architecture specifications
- Develop SystemVerilog RTL to implement logic for ASIC products
- Work with architecture and power teams to evaluate features and their impact
- Work with Design Validation (DV) teams to create test plans to verify and debug design RTL
- Work with physical design teams to ensure design meets physical requirements and timing closure
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science (preferred)
- Nice to have: High-performance ASIC design in Phase-Locked Loop
- Nice to have: Frequency-Locked Loop
- Nice to have: Delay-Locked Loop integration