Odin Dynamics is hiring multiple Senior Electrical Engineers to serve as Responsible Engineers for critical electrical subsystems across our platform, focusing on high-speed digital electronics, motor-control, or battery/power electronics.
Responsibilities
Serve as the Responsible Engineer for a major electrical subsystem.
Develop greenfield electrical hardware from initial requirements and architecture through field-tested, production-ready implementation.
Own schematic design, PCB layout, component selection, design reviews, analysis, bring-up, validation, production support, and sustaining improvements.
Design high-reliability electronics for systems with strict size, weight, power, thermal, performance, and environmental constraints.
Create electrical architectures and hardware interfaces in close collaboration with Embedded Software, Avionics, Power Electronics, Mechanical Engineering, Manufacturing Engineering, Supply Chain, and Test Engineering.
As a Digital Design Engineer, you'll join the team that designs the DSP cores and baseband hardware accelerators behind our next-generation modem products. Working alongside senior designers, you'll take on well-defined blocks and grow into the full design flow, from specification and RTL to synthesis and timing.
Responsibilities
Write and debug RTL (Verilog/SystemVerilog) for blocks within 5G baseband DSP cores and hardware accelerators, under the guidance of senior engineers.
Translate block-level specifications into clean, well-documented, synthesizable designs.
Run lint, synthesis and timing analysis on your blocks, and help resolve the issues they raise.
Support verification engineers in bringing up testbenches, debugging failures and reaching coverage goals.
Take part in design reviews and learn to weigh power, performance and area (PPA) trade-offs.
A Design/SDC Engineer focused on timing constraints, SDC/STA tools, and seamless physical design closure for next-generation networking chips.
Responsibilities
Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Requirements
Bachelor’s Degree in Electrical or Computer Engineering
Master’s Degree in Electrical or Computer Engineering
Lead design of high‑speed analog mixed‑signal circuit blocks for Serdes transceivers, including DAC/ADC, clocking, and analog front‑end components, and drive silicon productization from design through validation.
Responsibilities
Own performance‑critical analog mixed‑signal circuit blocks used in Serdes
Define circuit‑driven micro‑architectures of Tx and Rx subsystems
Own power, performance, area, and jitter budgets of analog design blocks
Mentor sub‑block owners and conduct peer reviews of design and verification results
Work with pre‑tapeout verification and post‑silicon validation teams to bring up silicon and analyze results
Requirements
Ph.D. in Electrical Engineering or a related field
M.S. with relevant industrial experience in optical and/or electrical transceiver design
Nice to have: 200G+ CMOS transceiver design
Nice to have: silicon productization from design to mass production
Electrical Engineer responsible for non-RF electronics design for Prism antenna, including digital compute, power, embedded, and mixed-signal hardware.
Responsibilities
Own the electrical design of Prism's non-RF electronics: high-speed digital, power electronics, embedded control, and mixed-signal circuits
Architect and design high-density boards built around FPGAs, microcontrollers, high-speed data converters, and their peripherals, including DDR memory, multi-gigabit SerDes, and 10/100G Ethernet
Define clocking architectures: reference selection, clock distribution, jitter budgets, and synchronization across boards and subsystems
Design power trees end to end, from input power and conversion stages to point-of-load regulators, sequencing, monitoring, and protection
Design mixed-signal interfaces between digital and analog/RF domains, including ADC/DAC front ends, control loops, and sensor and telemetry circuits
Requirements
Bachelor's degree in electrical engineering or a related engineering discipline
Lead technical design and support for media systems across Netflix’s global creative spaces, focusing on audio, video, and networking infrastructure.
Responsibilities
Serve as a subject matter expert in image, sound, and integrated system design across Netflix’s global portfolio of specialty creative spaces
Own a deep understanding of industry standards, emerging technologies, and best practices across room types
Translate creative and technical requirements into clear system designs and project-level specifications
Partner with construction teams, architects, and subcontractors to inform technical requirements
Maintain and troubleshoot complex audio, video, and networking systems across post-production facilities, theatrical screening rooms, QC environments, and creative spaces
The Technician I Production performs calibration and functional tests on subassemblies and end items of moderate complexity in accordance with established procedures.
Compensation
24.64 - 32.47
Responsibilities
Perform assigned testing operations within assigned functional area
Create non-conformance reports including detailed description of testing performed, resulting failure and initial root cause investigation results
Interpret and work in accordance with work orders, engineering drawings, functional and acceptance test procedures, failure reports, manuals and other applicable engineering and production specifications
Calibrate or otherwise adjust assigned units by such means as potentiometer adjustment, clocking or other positioning, shimming, tension or coil adjustments, bearing and gear adjustments, as appropriate for specific unit; Make required mathematical calculations for voltage, resistance, current, impedance, amplification, flow rate and mass, mechanical dimensions and adjustments
Perform automated testing and performance testing using a variety of automated testing equipment and special test console to simulate in-service specifications, including but not limited to: vibe, burn in, thermal cycle and leak test, or hydraulic testing
Oversees definition, design, verification, and documentation for SoC development, driving architecture, design, implementation, and optimization of complex digital logic for next-generation NAND Flash memory–based SSD controllers.
Compensation
The compensation range for this role is $167,360 - $267,800.
Responsibilities
Architect, design, and implement complex RTL modules using Verilog/SystemVerilog
Translate system and microarchitecture specifications into efficient, synthesizable RTL
Design and optimize controller pipelines, state machines, arbitration logic, queues, FIFOs, DMA engines, and memory interfaces
Develop and optimize hardware logic for NAND command sequencing, interface control, data transfer, status handling, error recovery, and timing management
Requirements
Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Collaborating with the logic design team to understand partition architecture and proactively addressing physical design aspects early in the development cycle.
Compensation
The base pay range for this role is between $174,149 - $225,300/yr
Responsibilities
Managing the complete netlist-to-GDSII implementation process for design partitions
Ensuring project schedules and design objectives are met
Performing timing analysis, physical and electrical verification, and driving signoff closure for the partitions
Working closely with the architecture team to define, analyze, and document the micro-architecture specifications of various hardware design blocks
Conducting feasibility analyses on proposed architectures and algorithms
Requirements
Master’s Degree in Electrical and Computer Engineering or related field
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