Principal Design Engineer
Astera Labs · San Jose, US· Principal
Director, ASIC Verification
International Recruiting LLC · Santa Clara, US+1 more On-site · Full-time · Manager
Principal Digital Design Engineer
Astera Labs · San Jose, US· On-site · Full-time · Principal
+10K new in the last hour
Astera Labs · Posted Nov 6, 2026
Lead design of high-performance network controller front-end circuits, overseeing architecture, RTL, synthesis, verification, and silicon bring-up.
The base salary range is $185,000.00 USD – $240,000.00 USD.
Develop micro-architecture and front-end circuit design for network controllers Write RTL, perform synthesis, timing closure, and GLS Integrate IP blocks and conduct block-level verification Drive designs from architecture to GDS and production Collaborate with customers and cross-functional teams Bachelor’s degree in Electrical Engineering Master’s degree in Electrical Engineering (preferred) Nice to have: firmware development in C Nice to have: Python scripting International Recruiting LLC · Posted Nov 5, 2026
Lead ASIC verification strategy, sign-off, and team management while performing hands‑on verification engineering.
Santa Clara, California, United States Cambridge, Massachusetts, United States Competitive salary with performance-based bonus and early-stage equity grant
Own verification end‑to‑end strategy and methodology Architect and author verification environments and testplans Review testbench code line‑by‑line Drive debug of hardest protocol, coverage, and bring‑up issues Recruit, lead, and develop a world‑class verification organization BS/MS in Electrical Engineering, Computer Engineering, or related field Nice to have: PhD in EE/CE Nice to have: startup experience building verification team Nice to have: AI/datacenter accelerator background Astera Labs · Posted Nov 2, 2026
We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers.
The base salary range is $185,000.00 USD – $230,000.00 USD.
Developing micro-architecture and implementation of the front-end circuit design RTL, synthesis, IP integration, and block-level verification for high performance network controllers Full chip or block level ownership from architecture to GDS Driving multiple complex designs to production Bachelor’s degree in Electrical Engineering Nice to have: Firmware development with C-language Nice to have: Python Nice to have: PCIe or Ethernet Switch products
Nice to have: LLM memory/dataloader bottlenecks 100% employer‑paid Health, Dental, Vision 401(k) match with immediate vesting Life, Disability, AD&D insurance fitness stipend wellness & mental health perks
