- San Jose, California, United States
- Full-time · Senior
- $232K–$330K per year
- 15+ years
Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.
Compensation
$231,500 - $330,000 USD
Responsibilities
- Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems
- Define comprehensive verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives
- Architect and develop scalable, reusable SystemVerilog/UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models
- Establish and advance verification methodology, coding standards, testbench guidelines, regression practices, and automation that improve consistency, quality, reuse, debug efficiency, and predictability across programs
- Drive verification closure using functional, code, assertion, and cross coverage; identify coverage gaps, evaluate risk, and ensure readiness against defined exit criteria
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
- Nice to have: verifying FPGA architectures
- Nice to have: programmable-logic devices