Contribute to the design, development, verification, and validation of airborne radar hardware for defense and aerospace applications. Focus on RTL development, FPGA/ASIC design, simulation, and hardware bring-up.
Compensation
The salary range for this role is 75,800 USD - 144,200 USD.
Responsibilities
Design and implement digital hardware blocks using Verilog/SystemVerilog or VHDL
Develop RTL for FPGA and/or ASIC-based systems
Participate in architecture discussions and technical design reviews
Create and execute simulation testbenches for functional verification
Debug RTL, simulation, synthesis, and hardware integration issues