Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
Develop diagnostic databases, software and hardware for logic and memory fail debug.
Design and implement system level test strategy.
Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
Lead and manage execution of multiple semiconductor IP programs, aligning with strategic goals and driving operational excellence.
Locations (2)
Mississauga, Ontario, Canada
Sunnyvale, California, United States
Compensation
Base Salary Range: $188600 - $282900
Responsibilities
Lead and manage execution of multiple programs in technology enablement, IP process and operations, and development and deployment of digital and analog methodologies.
Collaborate with technical leaders across engineering disciplines and product teams.
Align program objectives with company strategic goals and vision.
Define program objectives, scope, and deliverables.
Develop and maintain comprehensive program plans.
Requirements
Bachelor's or master's degree in a relevant field (Computer Science, Data Science, or related discipline)
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