Senior ASIC Verification Engineer to join networking silicon development team
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 158,500 - 321,000 in California
- Own and drive block-level or subsystem verification efforts
- Develop, enhance, and maintain advanced UVM verification environments
- Perform constraint-driven random testing, debug complex SoC designs
- Analyze simulation results using industry-leading simulation tools
- Collaborate with cross-functional teams to identify and resolve issues
- Nice to have: verifying networking ASICs
- Nice to have: router datapath/control blocks
- Nice to have: high-speed interconnects
- Nice to have: buffers
- Nice to have: scheduling pipelines
Sr. Silicon Design EngineerAdvanced Micro Devices, Inc · Orlando, US