Referso Jobs

Launch Engineer II - Pneumatics

BLUE ORIGIN · Posted Nov 11, 2026

Open

Florida, United States
2+ years

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Launch Engineer II - Pneumatics

BLUE ORIGIN · Posted Nov 11, 2026

Open

Florida, United States
2+ years

Apply with RefersoAI Apply on careers page

Product Technical Lead

Darlington Building Society · Posted Nov 11, 2026

Open

Hybrid
Full-time · Senior

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A specialist and influential role where you’ll take technical ownership of how our savings and mortgage products are designed, configured, tested, launched and maintained across our technology estate.

Compensation

Competitive salary, regularly benchmarked against the role, sector and local market.

Responsibilities

Taking technical ownership of how our savings and mortgage products are built, configured, maintained and distributed across our core banking, digital, mortgage origination and data platforms.
Managing and coordinating product builds to ensure new products and changes are delivered accurately and to agreed launch dates.
Configuring and overseeing product features including interest rates, tiers, terms, notice periods, ISA rules, fees, charges, redemption terms and early repayment charges.
Leading end-to-end product testing, quality assurance, change control, launch readiness and post-launch validation.
Owning and maintaining product blueprints, technical documentation, product records and capability maps.

Requirements

relevant qualification or equivalent practical experience in product management, business analysis, technology, software testing, change delivery or agile product ownership
Nice to have: experience within a building society
Nice to have: experience within a bank
Nice to have: experience within a mortgage lender
Nice to have: experience within a savings provider

Full Stack Programmer

NetApp, Inc. · Posted Nov 11, 2026

Open

Bangalore, India
4+ years

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Oracle CPQ Developer responsible for configuring, developing, testing, and supporting Oracle CPQ Cloud solutions for product configuration, pricing, quoting, and order management processes.

Responsibilities

Configure Oracle CPQ product models, attributes, constraints, and validation rules
Support enhancements and bug fixes in Oracle CPQ applications
Create and maintain Commerce rules such as validation, hide/show, filter, and constraint rules
Develop and maintain BML scripts for pricing calculations, discount logic, commerce actions and defaulting & validation rules

Requirements

Bachelor of Engineering in Computer Science, Information Technology or related field
Nice to have: Oracle CPQ Cloud Certification

Skills

Oracle CPQ Cloud configuration and development BML (Big Machines Language)product models, attributes, rules, constraints, and validations pricing rules, discounting logic Commerce processes

Digital Design Implementation Engineer

Leadstack Inc · Posted Nov 10, 2026

Open

San Jose, California, United States
2+ years

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Digital Design Implementation Engineer

Responsibilities

Perform ASIC design implementation in logic synthesis, static timing analysis, and place and route
Develop and maintain implementation flows and scripts, and drive timing, power, and area closure
Perform timing signoff, including constraint development and checking, and resolve timing violations
Work with RTL design, DFT, and physical design teams to resolve implementation issues
Support silicon bring-up and commercialization

Requirements

BS or BE minimum in Electrical/Computer Engineering or a related field
Nice to have: Experience implementing high-speed designs such as SerDes/high-speed PHY or high-frequency digital blocks
Nice to have: Experience with advanced process nodes, clock tree synthesis, and multi-corner/multi-mode timing closure
Nice to have: Familiarity with low-power design methodology (UPF) and signoff checks (physical verification, IR/EM)

Skills

ASIC design implementation logic synthesis static timing analysis

ASIC Design Technical Lead (CPU subsystems)

Cisco · Posted Nov 9, 2026

Open

San Jose, California, United States
$187K–$268K per year
3+ years

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Lead the architecture and design of complex CPU subsystems for next-generation high-performance networking switch ASICs.

Compensation

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Responsibilities

Lead architecture and design of CPU subsystems
Use expertise in all stages of ASIC development from specification and RTL design through post-silicon bring-up
Collaborate closely with SDK, board-support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models
Support early emulation and FPGA platforms

Requirements

Bachelor’s + 8 years of related experience
Master’s + 6 years of related experience
PhD + 3 years of related experience
Nice to have: CPU/SoC subsystem architecture
Nice to have: high-performance networking or data-center SoCs

Skills

RISC-V ARM ARC AXI

FPGA Development Lead

Firefly Aerospace · Posted Nov 5, 2026

Open

Cedar Park, Texas, United States
8+ years

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Lead FPGA design and development for Firefly Aerospace launch vehicles, spacecraft, and ground systems.

Responsibilities

Provide technical direction and mentorship to FPGA engineers
Drive adoption of best practices in FPGA development, reliability, and design verification
Own significant portions of FPGA designs from concept through implementation, timing closure, lab bring-up, integration, and verification
Help establish and refine clear FPGA development processes
Work closely with embedded software, hardware engineering, systems engineering, and other stakeholders to ensure seamless integration of FPGA designs

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
Nice to have: Master’s degree in Electrical Engineering, Computer Engineering, or related field
Nice to have: high-speed interfaces
Nice to have: SERDES
Nice to have: PCIe

Skills

VHDL Verilog SystemVerilog FPGA architectures timing closure

Launch Engineer II - Pneumatics

Launch Engineer II - Pneumatics

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Product Technical Lead

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Full Stack Programmer

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Digital Design Implementation Engineer

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ASIC Design Technical Lead (CPU subsystems)

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FPGA Development Lead

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Constraints jobs

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