Constrained-random testing jobs

Functional Verification Engineer

Accenture Infrastructure and Capital Projects, LLC · Posted Nov 4, 2026

Bengaluru, Karnataka, India
On-site
Full-time · Senior
5+ years

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Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM.

Responsibilities

Expected to be an SME, collaborate and manage the team to perform.
Responsible for team decisions.
Engage with multiple teams and contribute on key decisions.
Provide solutions to problems for their immediate team and across multiple teams.
Lead efforts to improve verification methodologies and processes to enhance efficiency and coverage.

Requirements

15 years full time education
Nice to have: PCIe Subsystem/SoC DV
Nice to have: Ethernet/Networking SoC DV
Nice to have: Embedded C
Nice to have: Firmware validation

Skills

SoC Verification SystemVerilog UVM constrained-random testing coverage-driven verification Xcelium

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Benefits

Functional Verification Engineer

Responsibilities

Requirements

Skills