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Skill:cross capacitance

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1–3 jobs· newest first

Layout/Mask Designer
Apple · Beaverton, US
On-site · Full-time
Layout/Mask Design
Apple · Austin, US
On-site
PMU Analog Layout Designer
Apple · Austin, US+1 more
On-site · Full-time · Associate

+10K new in the last hour

Layout/Mask Designer

Apple · Posted Nov 5, 2026

Beaverton, Oregon, United States
On-site
Full-time
2+ years

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AI

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Design complex custom layout for digital circuits in deep SubMicron CMOS technologies, review and analyze floorplans, run layout verification tools, and collaborate with circuit designers to optimize layouts.

Responsibilities

Design complex custom layout for digital circuits in deep SubMicron CMOS technologies
Review and analyze floorplans and complex circuits with circuit designers
Run a complete set of layout design verification tools on megacells
Plan, schedule work and negotiate layout tradeoffs with the circuit design team
Analyze LVS, DRC and ERC reports to find the fastest way to complete layouts

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering or related field

Skills

layout floor-planning standard cell planning hierarchical layout assembly RC delay understanding electromigration self-heating cross capacitance wire planning power grid design IR simulation tools DRC & LVS report interpretation Cadence Virtuoso layout design tools circuit and layout knowledge for low noise, low power data paths and memory layout structures Cadence Virtuoso EMIR DRC LVS P&R tools

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Layout/Mask Design

Apple · Posted Nov 5, 2026

Austin, Texas, United States
On-site
2+ years

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Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.

Responsibilities

Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.
Work with Layout lead and circuit designers to review and analyze floorplans of complex circuits.
Responsible to run a complete set of layout design verification tools available and clean up megacells to match engineering specifications.
Work with Layout lead and circuit design team to plan, schedule work and negotiate layout tradeoffs as needed.
Interpret LVS, DRC and ERC report to find the fastest way to complete layouts.

Requirements

Bachelor's degree in Electrical Engineering

Skills

layout floor-planning standard cell planning hierarchical layout assembly RC delay electromigration self-heating

PMU Analog Layout Designer

Apple · Posted Nov 3, 2026

Austin, Texas, United States +1 more
On-site
Full-time · Associate
3+ years

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Design and deliver high-performance analog layout for PMU and chip-level IPs.

Locations (2)

Austin, Texas, United States
Cupertino, California, United States

Responsibilities

Deliver PDV clean layout
Plan and schedule work with circuit design team
Recognize failure-prone circuit and layout structures
Run design verification tools on Mega-cell and chip level
Interpret LVS, DRC and ERC reports

Requirements

BS in relevant field
Master's Degree preferred

Skills

analog/mixed-signal layout design SubMicron CMOS tight matching

cross capacitance

shielding critical signals

CADENCE virtuoso

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low capacitance

low power analog blocks

high voltage devices

custom and standard cell floor planning

hierarchical layout assembly

electro-migration

cross capacitance

analog and DFM practices

PMU and chip level layout

Scripting in PERL or SKILL CODE

interpretation of Calibre, DRC, ERC, LVS reports

MENTOR GRAPHICS or CADENCE layout tools

MENTOR GRAPHICS

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