Referso Jobs

Principal Physical Design Engineer - SoC Floorplanning & Methodology

Microsoft · Posted Nov 6, 2026

Open

London, England, United Kingdom
Senior
£94K–£162K per year

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Principal Physical Design Engineer - SoC Floorplanning & Methodology

Microsoft · Posted Nov 6, 2026

Open

London, England, United Kingdom
Senior
£94K–£162K per year

Apply with Referso

Layout/Mask Designer

Apple · Posted Nov 5, 2026

Open

Beaverton, Oregon, United States
On-site
Full-time
2+ years

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Design complex custom layout for digital circuits in deep SubMicron CMOS technologies, review and analyze floorplans, run layout verification tools, and collaborate with circuit designers to optimize layouts.

Responsibilities

Design complex custom layout for digital circuits in deep SubMicron CMOS technologies
Review and analyze floorplans and complex circuits with circuit designers
Run a complete set of layout design verification tools on megacells
Plan, schedule work and negotiate layout tradeoffs with the circuit design team
Analyze LVS, DRC and ERC reports to find the fastest way to complete layouts

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering or related field

Skills

layout floor-planning standard cell planning hierarchical layout assembly RC delay understanding electromigration self-heating

Layout/Mask Design

Apple · Posted Nov 5, 2026

Open

Austin, Texas, United States
On-site
2+ years

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Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.

Responsibilities

Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.
Work with Layout lead and circuit designers to review and analyze floorplans of complex circuits.
Responsible to run a complete set of layout design verification tools available and clean up megacells to match engineering specifications.
Work with Layout lead and circuit design team to plan, schedule work and negotiate layout tradeoffs as needed.
Interpret LVS, DRC and ERC report to find the fastest way to complete layouts.

Requirements

Bachelor's degree in Electrical Engineering

Skills

layout floor-planning standard cell planning hierarchical layout assembly RC delay electromigration self-heating

AI Accelerator Physical Design Engineer

RosaicLabs · Posted Oct 5, 2026

Open

Santa Clara, California, United States
On-site
Full-time · Senior
5+ years

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Lead the physical implementation of accelerator blocks and top-level designs, managing synthesis, floorplanning, power planning, placement, clock tree synthesis, routing, and verification to meet PPA targets.

Responsibilities

Own physical implementation of accelerator blocks and top level
Develop floorplans for repeated compute tiles, large SRAM arrays, and high-bandwidth data movement
Close timing, power, and area targets
Manage power delivery and density
Implement low-power techniques

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field

Skills

high performance physical design low power physical design synthesis place-and-route signoff timing closure clocking static timing analysis

Electromigration jobs

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