- Penang, Malaysia
- Senior
- 7+ years
Senior IP Design Engineer responsible for building Connectivity IP portfolios for Lattice FPGA, translating specifications into high-speed RTL design and ensuring performance, power, and logic utilization.
Responsibilities
- Translate specifications into high-speed RTL design
- Collaborate with architects to develop Connectivity IP portfolios
- Ensure performance, power, and logic utilization
- Perform verification, debug, and timing closure
Requirements
- BS/MS/PhD in Electronics or Computer Engineering