Lead technical strategy and architecture for AI infrastructure networking at Microsoft.
Compensation
Technical Program Management IC6 - The typical base pay range for this role across the U.S. is USD $165,600 - $296,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year.
Responsibilities
Define the technical strategy and multi-year AI architecture direction for networking capabilities supporting Microsoft’s large-scale AI training and inference infrastructure
Provide technical leadership across complex AI infrastructure systems spanning GPU and accelerated computing infrastructure, systems software, telemetry, and operations into scalable end-to-end solutions
Translate AI workload requirements into system and networking architecture requirements spanning bandwidth, latency, topology, congestion management, resiliency, security, observability, serviceability, and operational efficiency
Lead technical evaluation and architectural decision-making across technologies including InfiniBand, RDMA, advanced Ethernet fabrics, network interface devices, switches, optics, cables, GPU interconnects, and emerging AI networking technologies
Create clarity in highly ambiguous problem spaces by driving alignment on complex architectural decisions and technical tradeoffs across networking, hardware and software engineering, systems architecture, datacenter infrastructure, operations, supply chain, finance, and customer-facing organizations
Field CTO - AI Infrastructure & Neocloud, Americas (Bay Area-based)
Seeking a visionary and technically deep Principal Product Manager to drive the strategy, roadmap, and lifecycle execution for flagship modular chassis platforms, specifically focusing on the PA-7500 Series Next-Generation Firewalls (NGFW).
Compensation
$176,800.00 - $286,000.00/yr
Responsibilities
Define the long-term vision, roadmap, and hardware platform strategy for the PA-7500 modular chassis portfolio and next-generation high-end hardware platforms.
Partner closely with hardware, ASIC/FPGA, and software architecture teams to define specifications for compute engines, network switch fabrics, memory subsystems, and high-speed optics/interconnects.
Drive requirements for custom ASICs, hardware offload engines, and crypto acceleration to deliver multi-terabit L7 inspection, App-ID, and Threat Prevention performance.
Author crisp, comprehensive Product Requirement Documents (PRDs) and user stories.
Lead cross-functional execution across hardware engineering, board design, firmware, thermal/power engineering, PAN-OS, and QA teams from concept through End-of-Life.
Requirements
Bachelor’s degree in Electrical Engineering
Bachelor’s degree in Computer Engineering
Bachelor’s degree in Computer Science
Nice to have: Master’s degree in Electrical/Computer Engineering
Nice to have: MBA
Skills
Requirements
Bachelor's Degree
Nice to have: 15+ years experience engineering
Nice to have: 10+ years managing cross-functional projects
Nice to have: 6+ years designing distributed large-scale datacenter
Nice to have: 6+ years deep technical experience with high-performance networking technologies
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