- Cupertino, California, United States +1 more
- On-site
- Full-time
- $150K–$225K per year
Contribute to all phases of the physical design of high-performance PHY design from RTL to delivery of final GDSII.
Locations (2)
- Cupertino, California, United States
- United States
Compensation
base pay range for this role is between $150,400 - $225,300/yr
Responsibilities
- Generate block/chip level static timing constraints
- Build full chip floor-plan including pin placement, partitions and power grid
- Develop and validate high performance low power clock network guidelines
- Perform block level place and route and close the design to meet timing, area and power constraints
- Generate and implement ECOs to fix timing, noise and EM IR violations
Requirements
- Master's degree or foreign equivalent in Electrical Engineering or related field