- Redmond, Washington, United States +1 more
- On-site
- Principal
- $143K–$275K per year
- 3+ years
Lead design and development of custom silicon IP for Microsoft’s Azure Cobalt chips, collaborating across architecture, firmware, verification, and physical design teams to deliver high‑performance, power‑efficient RTL and FPGA solutions.
Locations (2)
- Redmond, Washington, United States
- United States
Compensation
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Responsibilities
- Own and lead FPGA design environment efforts for rapid IP prototyping and design validation including root‑cause analysis of complex system issues.
- Own development of custom IP RTL from microarchitecture through RTL implementation, verification, and post‑silicon validation.
- Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high‑quality FPGA and IP solutions.
- Develop high‑performance, power‑efficient RTL designs and drive PPA optimization across the design lifecycle.