Design and develop advanced components of the memory sub-system and related logic for Microsoft’s cloud hardware infrastructure.
Compensation
Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year.
Responsibilities
Be part of a design team developing advanced components of the memory sub-system
Develop automation and AI based solutions to improve organizational efficiency
Own design blocks within complex, coherent fabrics, and bridge IPs
Be responsible for all aspects of the design flow including RTL coding, Lint, CDC, timing closure, etc
Collaborate with team members to define interfaces and make optimal design choices
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, or related field
Senior Applied Solution Engineer combining technical building skills with customer empathy and business acumen to deliver AI-powered solutions for SMB customers in EMEA Central.
Responsibilities
Coordinate and lead the entire solution cycle through close collaboration with other teams
Attain quarterly and annual objectives assigned by management
Maintain operational hygiene by documenting contribution
Build working prototypes, POC ready, and have reference architectures hands‑on
Advise as the technical trusted advisor for strategic accounts
Perform decontamination, preparation, sterilization and distribution of surgical instruments and medical equipment throughout RiverView Health.
Compensation
Pay Range: $20.89 - $27.02 (D.O.E - dependent upon experience)
Responsibilities
Operates all required equipment and machinery accurately and safely
Prepares, assembles, and sterilizes instruments and supplies according to parameters of sterilization in accordance with The Department of Health, TJC, OSHA, CDC, AAMI and AORN standards
Maintains appropriate records, and monitors quality control and infection control standards
Provides asset management and support of surgical instruments and trays belonging to or consigned to the facility
Correctly peel-packs supplies/instruments, wraps instruments for sterilization, inspect each instrument for use, function, completeness and cleanliness
Develops, coordinates, and leads standardized orientation, training, continuing education, and competency programs for team members who reprocess reusable medical devices across Mercyhealth.
Compensation
PAY RANGE: $22.73 - $32.96
Responsibilities
Develops and implements system-wide sterile processing and high-level disinfection education plan and training curriculum for onboarding and ongoing staff development in hospital and clinic settings.
Develops, reviews, and updates system-wide policies and procedures regarding sterile processing and HLD and provides appropriate education to staff.
Conducts audits to monitor compliance with policies and procedures and manufacturer’s written instructions for use (IFU).
Collaborates with SPD System Manager, SPD System Director, Infection Prevention staff, and hospital and clinic leadership to develop and implement quality assurance and performance improvement activities.
Visits all Mercyhealth Sterile Processing Departments at a minimum quarterly.
Design and implement power management, reset, and clocking solutions for RISC-V CPU and SoC IP.
Compensation
Base Pay Range
$205,740.00-$251,460.00
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Responsibilities
Work with the architecture team to understand and define power management requirements.
Architect, design and implement core clocking, reset and power management solutions.
Microarchitecture development and specification. Ensure that knowledge is shared via clear documentation and participation in a culture of collaborative design.
Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
Work with a physical implementation team to implement and optimise physical design to meet frequency, area, power goals.
Requirements
BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.
Nice to have: AMBA Interconnect Protocols such as AXI, AHB, and APB
Nice to have: AMBA Low Power Protocol Interface including P-channel and Q-channel protocols
Nice to have: Scala/Chisel, Bluespec, or other language/DSL for expressing configurable hardware via software
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