Lead RTL Design Engineer for Mixed‑Signal IPs, responsible for developing, integrating, and verifying digital RTL blocks within mixed‑signal subsystems.
Responsibilities
Develop synthesizable, high‑quality RTL for mixed‑signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front‑ends.
Collaborate with analog design engineers to define digital‑analog interface specifications, control logic, and communication protocols.
Ensure correct functionality and performance of mixed‑signal IPs through behavioral modeling, simulation, and co‑verification with analog components.
Participate in design reviews, micro‑architecture definition, and documentation of IP functionality and timing interfaces.
Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses.
Requirements
B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering
Define and document the microarchitecture for digital designs within the TPU
Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to achieve timing, area, power, and manufacturability goals
Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems
Support post-silicon validation and hardware debugging efforts to ensure successful deployment
Lead the development and enhancement of internal design tools, flows, and engineering methodologies
Work with the architecture team to understand and define power management requirements.
Architect, design and implement core clocking, reset and power management solutions.
Microarchitecture development and specification. Ensure that knowledge is shared via clear documentation and participation in a culture of collaborative design.
Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
Work with a physical implementation team to implement and optimise physical design to meet frequency, area, power goals.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or related technical discipline
Nice to have: Dynamic voltage and frequency scaling (DVFS)
Provides mid-level client support and back office fulfillment for basic Treasury Management products and services onboarding requests.
Compensation
Non-Exempt Hourly Rate: $20.50 – $30.50 per hour
Responsibilities
Provide fulfillment support for basic Treasury Management products and services including fulfillment of BOSS Events and supporting TM Support and Branch requests.
Continue to develop and learn all Treasury Management products and services, including Treasury Management setup, back office/client facing system functionalities.
Learn to support internal TMS Specialists and Call Center employees.
Support basic client’s on-boarding and maintaining new client relationships through the various department administrative systems.
Participate in supporting other department responsibilities to include projects and other duties as assigned.
A ProSearch Project Specialist Level 3 is a case assistant for a portfolio of client matters, working closely with project teams to ensure data is processed, reviewed, produced, and project-ready.
Compensation
The anticipated salary range for this position is 1500000INR = 2000000INR annually, with actual starting pay determined based on relevant experience, skills, qualifications, and other job-related factors.
Responsibilities
Work with Project Managers to support active client projects ensuring project requirements and deadlines are met
Work closely with internal team members and other departments to ensure that project goals and milestones are accomplished
Work with third party vendors to support client engagements
Experience with Relativity to design and modify databases, create complex searches and resolve technical issues
Good in understanding RTL Design and Digital concepts
Subsystem or SoC integration
Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc.
SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration
We are seeking an experienced Senior Eagle Developer / Eagle Data Vault Specialist responsible for development, enhancement, implementation, and production support of Eagle and Vault-based solutions.
Responsibilities
Design, develop, and enhance Eagle solutions across key product modules, including RDC, IWS, PDC, Message Center, Web Panels, Exporters/Uploaders, OLAP, Data Mart, Advanced Reports, and EDS.
Lead implementation and enhancement activities for Data Vault solutions, ensuring scalable and reliable delivery aligned with business and operational requirements.
Provide Level 2 production support for Eagle and Vault solutions, including incident analysis, issue resolution, root cause identification, and service stability improvements.
Work closely with business and technology stakeholders to understand requirements, propose effective technical solutions, and support successful delivery.
Perform analysis of Eagle data structures and business workflows to support solution design, troubleshooting, and optimization.
Define the Micro-architecture of the CPU hardware. Develop the CPU hardware using a Hardware-Description-Language. Perform functional debug and closure of the design. Responsible for timing and power closure of the design for the target Frequency and Power. Prepare documentation of the Design Specification. Design and develop hardware for Apple's mobile devices. Evaluate new ideas and features for the Central Processing Unit (CPU) hardware.
Compensation
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,294 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.
Responsibilities
Define the Micro-architecture of the CPU hardware
Develop the CPU hardware using a Hardware-Description-Language
Perform functional debug and closure of the design
Responsible for timing and power closure of the design for the target Frequency and Power
Prepare documentation of the Design Specification
Requirements
Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field
Highly experienced LINT, CDC, and RDC Verification Expert to drive methodology development, qualification, deployment, and signoff across complex SoC and IP programs.
Responsibilities
Define and maintain LINT, CDC, and RDC signoff methodologies for IP, Subsystem, and SoC development.
Drive deployment and qualification of EDA solutions across multiple projects.
Establish best practices, waiver management processes, and signoff criteria.
Lead technical reviews and provide guidance on structural verification issues.
Perform RTL quality checks using Questa Lint and VC SpyGlass Lint.
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