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1–2 jobs· newest first

DFT Lead Engineer
Broadcom · Austin, US
$144K–$230KSenior
DFT Engineer
Broadcom · Austin, US

+10K new in the last hour

DFT Lead Engineer

Broadcom · Posted Nov 6, 2026

Austin, Texas, United States
Senior
$144K–$230K per year
10+ years

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Lead DFT Engineer responsible for DFT programs from specification to production for Broadcom ASIC products.

Compensation

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

Responsibilities

Leading DFT programs from chip level specification to implementation and verification
Defining DFT specifications for ASICs
Implementing DFT including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Working closely with STA and DI Engineers for test closure
Generating, verifying and debugging test vectors before tape release

Requirements

Bachelor's in Electrical/Electronic/Computer Engineering
Master's in Electrical/Electronic/Computer Engineering

Skills

DFT background Scan insertion and scan compression ATPG vector generation Verilog coding Testbench generation Simulation Memory BIST insertion Boundary scan verification IEEE1149.1 IEEE1149.6 IEEE1687 IJTAG ICL PDL Analog and digital circuit design Device physics fundamentals Si processing Logical and physical synthesis Transistor reliability principles Debugging Root cause analysis TCL PERL RUBY PYTHON C++Verilog ATPG TetraMax Fastscan Mentor TestKompress

Benefits

Medical
Dental
Vision
401(K) participation with company matching
Employee Stock Purchase Program

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DFT Engineer

Broadcom · Posted Nov 6, 2026

Austin, Texas, United States
5+ years

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Design, implement, and verify DFT programs for Broadcom ASIC products.

Compensation

The annual base salary range for this position is USD To USD

Responsibilities

Understanding Broadcom & customer DFT feature requirements
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Working closely with STA and DI Engineers design closure for test
Generating, Verifying & Debugging Test vectors before tape release
Validating & Debugging Test vectors on ATE during the silicon bring up phase

Requirements

Bachelors in Electrical/Electronic/Computer Engineering
Masters Degree in Electrical/Electronic/Computer Engineering

Skills

TCL PERL RUBY PYTHON C++Verilog coding testbench generation & simulation

scan compression

ATPG vector generation

Memory BIST insertion

Boundary scan Verification

analog and digital circuit design

device physics fundamentals

logical and physical synthesis

transistor reliability principles

Mentor TestKompress

Benefits

Medical
dental
vision plans
401(K) participation
company matching

See full job description