Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.
Compensation
$231,500 - $330,000 USD
Responsibilities
Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems
Define comprehensive verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives
Architect and develop scalable, reusable SystemVerilog/UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models
Establish and advance verification methodology, coding standards, testbench guidelines, regression practices, and automation that improve consistency, quality, reuse, debug efficiency, and predictability across programs
Drive verification closure using functional, code, assertion, and cross coverage; identify coverage gaps, evaluate risk, and ensure readiness against defined exit criteria
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
Role focused on pre-silicon verification and post-silicon validation for custom silicon components powering Microsoft's cloud infrastructure.
Compensation
typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year.
Responsibilities
Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components.
Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
Develop Verification IP (VIP) components to verify home grown designs.
Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
Define and implement functional coverage and drive coverage closure.
