- Windsor, Connecticut, United States +1 more
- Senior
- $172K–$172K per year
- 2+ years
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Lead Engineer Design Verification
Salary $172,210
zTPF Developer
PCIe Verification Engineer
Design and implement ASIC/FPGA verification environments using UVM & SystemVerilog, develop testbenches, coverage models, and collaborate with cross‑functional teams.
Summary pay range for Associate (Leve 2): $85,850 - $116,150 Summary pay range for Experienced (Level 3) $104,550 - $141,450 Summary pay range for Lead (Level 4): $126,650 - $171.350
Develop and execute verification environments for complex semiconductor designs using SystemVerilog and UVM.
Baseband hardware engineer responsible for system integration, validation, and production support in wireless broadband communications.
Desarrollador Python con experiencia en Django y/o Falcon, responsable de crear y mantener APIs REST y microservicios.
Retribución flexible 💳: Tarjeta restaurante, cheque guardería, seguro médico, formación y otros beneficios con ventajas fiscales.
Lead technical design, code reviews, implementation approach, and engineering standards within the development team while guiding and mentoring engineers and QA team members on technical implementation, troubleshooting, best practices, and continuous improvement.
Review and analyze OEM-developed software documentation, code, and test reports to ensure compliance with security and quality standards.
The projected annual compensation range for this position is $100,000 - $140,000 (USD).